Self-calibrating asynchronous NoC links

Motivation With the advent of nanoscale technologies in semiconductors, the transistor dimensions have shrunk staggeringly. Forecasts indicate that by end of year 2010, multi-billion transistors with feature size of about 50nm and clock frequency more than 10 GHz will be under design [fSI08]. As number of functional blocks in a chip increases, delays in global wires become longer than the clock period. This drives the systems-on-chip (SoC) to be decomposed into several processing cores and IP blocks. In such complex systems, the conventional bus-based interconnects fail to achieve higher bandwidth and concurrent transmissions calling for the need of communication centric design. This lead to the adoption of a new communication architecture called Networks-on-chip (NoC) [BDM02]. In NoC paradigm, each processing element is interfaced through a resource network interface (RNI) to a switch. The adjacent switches are connected to each other via bidirectional links carrying the packets of information. Later, the increasing complexity and power consumption of clock networks in NoCs lead to several researches. One of the solutions is asynchronous NoC (ANoC) where emphasis is on the division of the complex system into several blocks driven by dierent clock sources. The major challenge in ANoCs is to connect such heterogeneous blocks together and ensure robust communication. The manufacturing processes have become more complex and are dicult to control due to miniaturization which makes on-chip communication less reliable. The miniatured wires at high speed become more vulnerable to process variations. In recent days, a large number of manufactured chips are dead in the water primarily due to timing violations and causing poor yield. The asynchronous design is a way to overcome the variation eects after fabrication and to salvage chips that would otherwise be thrown away. Shrinking interconnects impose limitation on operational margins of NoCs. This lays more responsibility on design techniques to exhibit robustness to the foreseeable variations in manufacturing of NoCs. Currently used traditional design practices are based on worst-case approach. Such conservative estimates limit the speed of operation in ANoCs and 1 increase energy consumption. That is, worst-case design leaves the component to operate at region well below its maximum capability in which case the benets of the technology generation are not fully utilized. As a solution, this report details Self-Calibrating Design which allows link to autonomously calibrate against process variations. Figure 1 illustrates the relationship between supply voltage and delay under three dierent perspectives. The curve Nominal …